To put it simply, one sentence: set the dual clock using the AXI STREAM FIFO.
How did I come to mind: Solving the preferred FIFO for asynchronous clock data transfer problems, and just one IP component of the AXI STREAM FIFO is available.
The full name of the IP core is: AXI4-STREAM FIFO
Setting precautions: Be sure to choose asynchronous clock, which is double clock, as follows:
Regarding other configurations: TLAST is generally chosen as a boundary definition. Others can not be selected. The depth does not have to be too deep, as it only serves to cross the clock area.
Example:
At the arrow, the two clocks M_AXIS_ACLK are the upstream clock, and S_AXIS_ACLK is the clock of the video part. For example, we use VGA 640*480 and the clock is 25M.
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