Due to its powerful function, flexible use, small size and high cost performance, the single chip microcomputer has been widely used in measurement and control systems in recent years. In many cases, the MCU acts as a lower-level machine, and is responsible for controlling data measurement, acquisition, and transfer to the host computer, that is, collecting, buffering, and storing data. The dynamic memory DRAM has the characteristics of large capacity and low price, and is suitable for a single-chip application system with a relatively large amount of data; however, the disadvantage is that the timing refresh must be performed within a prescribed time range. This section introduces a dynamic data buffer controlled by a single-chip microcomputer. By properly designing software and hardware, the control of DRAM can be realized, which is especially suitable for a cost-effective single-chip microcomputer system.
Control circuit
For convenience of explanation, a part of the circuit of the single chip system is given, as shown in FIG. The single-chip microcomputer adopts the 80 series of the 8031, the external expansion of the 16 KB EPROM, the dynamic memory uses 1 MB of the microcomputer memory, and the J1 is the socket and its pin signals. The 1 MB dynamic memory row and column address each use 10 bits, that is, 10 address lines A0 to A9 are used.
The control circuit of DRAM is shown in Figure 2. The core is a positive edge triggered double D flip-flop 74LS74, which is controlled by the 8031 ​​and TO, Tl, PSEN and EN, WR signals. When reading/writing data, TO and Tl are set to high level; when DRAM is refreshed, TO is set to 1 and PSEN is valid; when T0 and T1 are both set to 0, the row and column strobes are turned off, and DRAM read/write operations are prohibited.
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