MOS transistors are metal-oxide semiconductor semiconductor field-effect transistors, or metal-insulator-semiconductors. The source and drain of the MOS tube can be swapped. They are all N-type regions formed in the P-type backgate. In most cases, the two zones are the same, and even if the two ends are reversed, it will not affect the performance of the device. Such devices are considered symmetrical. At present, in the market applications, the number one consumer electronic power adapter products. The MOS tube applications ranked second in the computer motherboards, NB, computer adapters, LCD monitors and other products, with the development of national conditions, computer motherboards, computer adapters, LCD monitors demand for MOS tubes have to exceed consumer electronics Power adapter phenomenon. The third one belongs to the fields of network communications, industrial control, automotive electronics, and power equipment. The demand for these products for MOS transistors is also very large. In particular, the demand for MOS transistors in automotive electronics is now catching up with consumer electronics.
The following six points are summarized below for the causes of MOS failures.
1: Avalanche failure (voltage failure), that is, we often say that the BVdss voltage between the drain sources exceeds the rated voltage of the MOSFET and exceeds a certain level of power to cause the MOSFET to fail.
2: SOA failure (current failure), which exceeds the failure of the MOSFET safe operating area, is divided into Id exceeds the device specification failure and Id is too large, the loss caused by too long a device heat accumulation and failure.
3: Body diode failure: In a topology in which freewheeling diodes, such as bridges and LLCs, are used for freewheeling, the body diodes are destroyed due to failure.
4: Resonance failure: In the process of parallel use, the gate and circuit parasitic parameters cause the failure caused by the oscillation.
5: Electrostatic failure: In autumn and winter, the device fails due to static electricity in the human body and equipment.
6: Gate voltage failure: Since the gate is subjected to abnormal voltage spikes, the gate gate oxide layer fails.
Avalanche failure analysis (voltage failure)
What is avalanche failure in the end? Simply put, the MOSFET on the power board due to bus voltage, transformer reflected voltage, leakage inductance spike voltage system voltage is superimposed on the MOSFET drain source, resulting in a failure mode. In short, it is a common failure mode caused by the fact that the MOSFET drain-source voltage exceeds its specified voltage and reaches a certain energy limit. The following picture shows the equivalent schematic of the avalanche test. As a power engineer, you can easily understand the following.
Probably we often require device manufacturers to perform failure analysis on MOSFETs on our power boards. Most manufacturers only give a conclusion like EAS.EOS. So how do we distinguish whether it is an avalanche failure? The following is an avalanche. To test the failed device map, we can make a comparison to determine if it is an avalanche failure.
Avalanche failure preventive measures
Avalanche failure is ultimately a voltage failure, so prevention focuses on voltage considerations. Specifically refer to the following ways to deal with.
1: Reasonable derating use, the current industry derating generally choose 80% - 95% of the depreciation, the specific situation according to the company's warranty terms and circuit concerns selected.
2: a reasonable transformer reflection voltage.
3: Reasonable RCD and TVS absorption circuit design.
4: The large current wiring should adopt the thick and short layout structure as much as possible to minimize the parasitic inductance of the wiring.
5: Select a reasonable gate resistance Rg.
6: In a high-power power supply, RC snubbers or zener diodes can be properly added as needed.
SOA failure (current failure) and then the second point, SOA failure
SOA failure refers to the failure mode caused by the abnormally large current and voltage of the power supply superimposed on the MOSFET at the same time, causing transient local heating. Or the chip and the heat sink and the package can not reach the thermal equilibrium in time to cause heat accumulation, and the continuous heat generation causes the thermal breakdown mode caused by the temperature exceeding the limit of the oxide layer. About the parameter limit value of each line of SOA can refer to the following picture.
1: Limited by maximum rated current and pulse current
2: Limited by RDSON at maximum junction temperature.
3: Limited by the maximum power dissipation of the device.
4: Limited by the maximum single pulse current.
5: Breakdown Voltage BVDSS Restricted Area The MOSFET on our power supply can effectively avoid power failure due to the MOSFET as long as the device can be placed within the above limited range. This is a solution to the failure of an atypical SOA. Due to aluminum, it may not seem so straightforward. See below.
SOA failure prevention measures:
1: Ensure that all power limitations of the MOSFET are within the SOA limit line under worst-case conditions.
2: The OCP function must be precise and detailed. When designing an OCP point, engineers may generally take 1.1-1.5 times the current margin, and then start debugging the RSENSE resistor according to the IC's protection voltage, such as 0.7V. Some experienced people will take into account the delay in testing, CISS's actual impact on OCP. But there is a parameter that deserves more attention at this time, that is, the MOSFET Td(off). What effect does it have in the end? Let's look at the following FLYBACK current waveforms (the graphics are not too clear, I'm very sorry, it is recommended to double-click to zoom in to view).
It can be seen from the figure that the current waveform has a fall at the fast current spike, and there is a rise time after this fall point. The essence of this time is the IC's detection of the over-current signal after the shutdown. It also begins to perform shutdown itself, but due to the turn-off delay of the device itself, the current will have a secondary rise platform. If the secondary rise platform is too large, then magnetic saturation is very likely to occur if the transformer margin design is insufficient. One of the current surges or a failure of the current super device specification. 3: reasonable thermal design margin, this will not say more, each company has its own derating norms, strict implementation can be, and no heat radiator.
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