Today, advanced electronic systems for the telecommunications and datacom markets rely heavily on high-performance, fine-line digital ICs (FPGAs, DSPs, and/or ASICs) to process time-sensitive digital data quickly and efficiently. The need for higher bandwidth has forced manufacturers of these digital ICs to pursue leading-edge process technologies to optimize performance while minimizing power consumption. However, this trend has also created a variety of power management issues not found in previous generations of processes. Reducing the core voltage level and increasing the load current, the smaller chip size achieved by sub-100 nanometer process technology has dramatically increased the current density in these ICs. In addition, the use of separate voltage layers and multi-core architectures forces system designers to provide more unique voltage layers and to provide a specific ordering between these voltages. External power management ICs are available that address one or more of these high-end systems, but how to seamlessly work with these ICs and power conversion blocks is still an issue that needs to be addressed, often requiring multiple discrete components And a lot of software development.
Another tricky problem comes from unpredictable changes in the optimal operating parameters of the FPGA or ASIC. The resulting characterization results sometimes force designers to change their designs after building the initial hardware, making them difficult to decide in two ways: to capture the market opportunities they need with lower performance products, or Risk of delays that may give competitors a time-to-market advantage. Depending on the power architecture chosen, this change can be as complex as requiring additional voltage domains and new sequencing, as well as adjusting the system's hot operator face (operaTIng profile) to ensure higher total power consumption at the same location. Maintain reliability.
Point-of-load converters with integrated power management help system designers develop power system architectures with distributed intelligence. These architectures have higher performance and are easier to design than traditional analog power architectures. This intelligent power system also allows system designers to quickly adapt to changes in system requirements later in the development cycle, without significant hardware redesign or major software development delays, reducing time-to-market and enabling power system architecture Easily reused across a wide range of products with different power requirements.
PMBus achieves compatibility
To simplify the design of intelligent power systems, we must first provide a large number of compatible power products that require the flexibility and intelligence needed to implement complex power management functions while reducing the burden of combining different power components. To meet this requirement, several power ICs and power module companies created the Power Management Bus (PMBus), a standard set of instructions provided through the I2C or SMBus hardware interface. This open standard instruction set helps power component manufacturers (ICs and modules) to offer compatible products. These products can be easily integrated to create custom smart power architectures that previously required extensive design and customization of hardware and software. In addition, it provides standard PMBus commands to support multiple power management functions including voltage sequencing, margins, voltage, current and temperature monitoring, and extensive fault management. In addition, each PMBus command must be interpreted in the same way by any consistent device (regardless of manufacturer, form or power level), making it easy to extend simple system software work to include the required number of power domains.
System design example
Table 1 illustrates typical system power requirements for embedded telecommunications designs, as well as any management requirements associated with various power domains. Wide range of voltage and load currents, voltage requirements are required for test functions over the entire operating voltage range, and the voltage of each device must be dynamically controllable to optimize performance under various operating conditions. In addition, the voltage, current, and temperature of each load device must be monitored to provide accurate feedback on the normality of these high-performance, high-cost ICs and to ensure that the system operates within the specified temperature range. Mixing multiple high-density logic ICs also requires a unique combination of voltage sequencing and tracking. To achieve system compatibility and minimize input current through the backplane, we chose an input bus voltage of 12V. This design typically involves multiple power conversion ICs, multiple external power management ICs, and discrete components to implement sequencing, tracking, margining, and monitoring functions. But by using a PMBus-compatible product, the system can be easily built with a minimum of unique power conversion ICs and minimal device-to-device connections (shown in Figure 1).
For higher current supplies, we chose a single-phase PMBus DC/DC controller (ZL2005) because it can handle up to 30A of load current with flexibility, and it can transmit higher by paralleling multiple devices. Load current. For low current (less than 3A) supply, we chose a PMBus DC/DC converter (ZL2105) with integrated MOSFETs because of its small form factor. All the necessary power management features are integrated into each device, making it easy to configure each device's individual requirements while minimizing the number of discrete components and minimizing and general use Configure the tolerances associated with the R/C network of the analog power IC. In addition, each IC incorporates a highly accurate temperature sensor that enables ICs that power a particular load IC to monitor their temperature in real time.
No need to use sorter for sorting
One of the many unique features of these ICs is their ability to implement deterministic sequencing algorithms without the need for external sequencer ICs or software development. Each IC's output voltage rise duration can be set using a simple pin connection, and each power supply can be configured to start rising at a particular time or follow the output of another system voltage. Voltage tracking can also be easily configured by connecting the VTRK pin of the tracking device to the voltage to be tracked; consistent tracking or proportional tracking can be selected using the same pin connection method. Use this simple solution to quickly configure the entire system sort order and/or trace ratio without the need for host processor or software development. Figure 2 shows the final combination of multiple inter-voltage sequencing and consistent tracking.
Adapt to changes in system requirements
When powering high-performance digital ICs, such as FPGAs, DSPs, and ASICs, the voltage and sequencing requirements often change after initializing the hardware. For example, after initial testing, it was determined that system performance would meet the design goals only if the FPGA I/O supply was powered up the first time the logic supply was powered up or before the FPGA core was powered (as opposed to the original design assumptions). Implementing this change with traditional power management ICs will require hardware and system software changes that will lose critical market opportunities. But with power management ICs that support PMBus, these changes can be implemented with a few simple PMBus commands to reconfigure the ordering. System modifications are limited to very simple software changes, with no hardware changes, allowing designers to maintain the same project deadline. Figure 3 shows the new sort that has been quickly reconfigured.
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