Some time ago, I was playing xilinx and sent me to run XUPV5-LX110T. I first ran the demo design of XUPV5-LX110T given by xilinx. I found that I encountered some errors but I found very few answers on the Internet. Posted out:
(1) There was a problem with xupv5_bsb_std_ip and its error description is as follows:
[xupv5_bsb_system.ucf(1110)]: NET "xps_iic_0_Gpo_pin" not found. Please
Verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
IOSTANDARD=LVCMOS33;> [xupv5_bsb_system.ucf(1111)]: NET "xps_iic_0_Gpo_pin"
Not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
Make: *** [__xps/xupv5_bsb_system_routed] Error 1
Solution: Open the xupv5_bsb_system.mhs file in the xupv5_bsb_std_ip folder.
In its 80-line position, comment out PORT xps_iic_0_Gpo_pin = xps_iic_0_Gpo, DIR = O, VEC = [31:31] (ie add # in front) or delete.
At 551 lines, comment out PORT Gpo = xps_iic_0_Gpo (ie add # in front) or delete.
Save the file.
Then open the xupv5_bsb_system.ucf file in the xupv5_bsb_std_ip folder. At its 1110 and 1111 lines, Net xps_iic_0_Gpo_pin LOC=AK6; # DVI_RESET_B
Net xps_iic_0_Gpo_pin IOSTANDARD=LVCMOS33; two lines are deleted or commented out.
Save the file.
(2).Running DRCs for OSes, Drivers and Libraries ...
Runnning DRC for lwIP library...
ERROR:MDT - issued from TCL procedure "::sw_lwip_v3_00_a::lwip_drc" line 12
Lwip () - No Ethernet MAC cores are addressable from processor ppc440_0.
lwIP requires atleast one EMAC (xps_ethernetlite | xps_ll_temac) core.
ERROR:MDT - Error while running DRC for processor ppc440_0...
Make: *** [ppc440_0/lib/libxil.a] Error 2
Done!
When you see this problem, you must first learn to find it yourself. The obvious hint is lwip error. Let's look at the datasheet and find out: lwIP provides an easy way to add TCP/IP-based networking capability to an embedded systemlwip_v3_00_a in EDK provides adapters for the Xps_ethernetlite and xps_ll_temac
Xilinx? Ethernet MAC cores, and is based on the lwIP stack version 1.2.0. This document
How to use lwip_v3_00_a to add networking capability to embedded software. We know its role, then find it, anyway, xilinx is based on mhs and mss files, then action solution: find in the mss file # BEGIN LIBRARY
PARAMETER LIBRARY_NAME = lwip
PARAMETER LIBRARY_VER = 3.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER api_mode = SOCKET_API
END
Comment it out or delete it.
(3).ERROR: Failed to add write permission for
D:\..\microblaze_0\libsrc\lcd_ip_v1_00_a\
ERROR:Failed to copy
D:\..\drivers\lcd_ip_v1_00_a\src\ to
D:\..\microblaze_0\libsrc\lcd_ip_v1_00_a\
Copying files for driver cpu_v1_11_b from
D:\Xilinx\11.1\EDK\sw\XilinxProcessorIPLib\drivers\cpu_v1_11_b\src\ to
ERROR: Error while running "Copy Files" for processor microblaze_0...
Make: *** [microblaze_0/lib/libxil.a] Error 2
Done!
Solution: Go to the desktop and right click on My Computer, select Properties, then select the Advanced tab, click Environment Variables, under the New Environment Variables dialog box, click the New button for System Variables and enter the variable name: CYGWIN
Enter: nontsec in the variable value, click OK, restart XPS, recompile.
(4).ERROR:EDK - D:\Xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 392 - PARAMETER C_LEFT_POS has value 7 which does not fall in the range (0:C_SPLIT-1), specified in MPD
ERROR:EDK - D:\Xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 393 - PARAMETER C_SPLIT has value 31 which does not fall in the range (1:C_SIZE_IN-1), specified in MPD
ERROR:EDK - D:\Xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 392 - PARAMETER C_LEFT_POS has value 7 which does not fall in the range (0:C_SPLIT-1), specified in MPD
ERROR:EDK - D:\Xilinx\sample\xupv5_bsb_std_ip\xupv5_bsb_system.mhs line 393 - PARAMETER C_SPLIT has value 31 which does not fall in the range (1:C_SIZE_IN-1), specified in MPD
Solution: This error can be safely ignored as it is being in improperly. The project will implement.
The official reply is to ignore this error.
(5).WARNING:EDK:2099 - PORT:I_ADDRTAG CONNECTOR:ilmb_M_ADDRTAG -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_20_a\data\mic
Roblaze_v2_1_0.mpd line 232 - floaTIng connecTIon!
WARNING: EDK:2099 - PORT:D_ADDRTAG CONNECTOR:dlmb_M_ADDRTAG -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_20_a\data\mic
Roblaze_v2_1_0.mpd line 273 - floaTIng connecTIon!
WARNING:EDK:2099 - PORT:HostMiimSel CONNECTOR:host_mii_sel -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ll_temac_v2_00_a\data\x
Ps_ll_temac_v2_1_0.mpd line 264 - floating connection!
WARNING:EDK:2099 - PORT:HostReq CONNECTOR:host_req -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ll_temac_v2_00_a\data\x
Ps_ll_temac_v2_1_0.mpd line 265 - floating connection!
WARNING: EDK:2099 - PORT:HostAddr CONNECTOR:host_addr -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ll_temac_v2_00_a\data\x
Ps_ll_temac_v2_1_0.mpd line 266 - floating connection!
WARNING: EDK:2099 - PORT:HostEmac1Sel CONNECTOR:host_emac1_sel -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ll_temac_v2_00_a\data\x
Ps_ll_temac_v2_1_0.mpd line 267 - floating connection!
WARNING: EDK:2099 - PORT:bscan_tdi CONNECTOR:bscan_tdi -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 223 - floating connection!
WARNING: EDK:2099 - PORT:bscan_reset CONNECTOR:bscan_reset -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 224 - floating connection!
WARNING: EDK:2099 - PORT:bscan_shift CONNECTOR:bscan_shift -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 225 - floating connection!
WARNING: EDK:2099 - PORT:bscan_update CONNECTOR:bscan_update -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 226 - floating connection!
WARNING:EDK:2099 - PORT:bscan_capture CONNECTOR:bscan_capture -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 227 - floating connection!
WARNING: EDK:2099 - PORT:bscan_sel1 CONNECTOR:bscan_sel1 -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 228 - floating connection!
WARNING: EDK:2099 - PORT:bscan_drck1 CONNECTOR:bscan_drck1 -
D:\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v1_00_e\data\mdm_v2_1_0
.mpd line 229 - floating connection!
Solution: The official solution is to ignore warning and not affect the results.
(6).ERROR: 1 constraint not met.
PAR could not meet all timing constraints. A bitstream will not be generated.
To disable the PAR timing check:
1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS.
OR
2> Type following at the XPS prompt:
XPS% xset enable_par_timing_error 0
Solution: Select the project options in the XPS project menu bar and select hierarchy and Flow to
The timing closure failure as an error can be removed.
(7).ERROR: Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ<13>" and
IODELAY
Component
"DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
En_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other
Into
The same I/O tile in order to route net
"DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g
En_dq[13].u_iob_dq/dq_in". The following issue has been detected:
Some of the logic associated with this structure is locked. This should
Cause
The rest of the logic to be locked.A problem was found at site
IODELAY_X0Y56
Where we must place IODELAY
DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
N_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative
Placement
Requirements of this logic. IODELAY
DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge
N_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there
Which
Make this design unplaceable.
Solution: Open your project, in the system assembly view interface, switch to the ports column, the fpga_0_DDR2_SDRAM drop-down box, find the corresponding item, select the corresponding item.
Cable Assembly,Tv Adapter Connector,Audio Cable Connector,M12 4Pin Cable Assembly
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