The Xilinx Vivado tool supports the integration of only part of the system design, the OOC (out of context) synthesis. The process of the OOC integrated approach is to complete the integrated operation of a certain module of the design, which brings the following possibilities:
By integrating the rapid iteration of this module, the iteration of the entire design without the rest of the integrated system is faster.
Conducive to the rapid iteration of the rest of the system, if a certain part is determined to be stable, you can perform OOC synthesis on this module, retain this comprehensive version, so that it is easy to iterate the rest
The change of a module only needs to be integrated into this module, and the time saved is used for module function design.
The OOC synthesis method is very suitable for the design of IP cores. We can integrate our IP cores in OOC mode and use the combined output results.
This means that when we use IP cores, we don't need to perform integrated operations on IP cores to improve system design.
However, if there is a three-state (high-impedance state) in the design, the OOC synthesis operation will be affected.
The FPGA only supports the high-impedance state of the I/O output port, which is not allowed inside the device.
If you use OOC synthesis, the Vivado tool doesn't know if a specific signal is connected to the I/O output or connected inside the device.
Finally, the synthesis tool converts this high-impedance signal into a logical value instead of the most high-impedance state.
For example, the following code will have a bad effect:
Assign my_signal = enable?din1:1'bz;
After the OOC method is integrated, the my_signal signal value will not be high resistance value Z.
There are two options for Vivado synthesis:
1. The integrated operation is fully compliant with the HDL code. (When this module unit is connected to the rest, if this signal will be the most I/O output, then it will have no effect)
2. Do not retain three states
The Vivado tool will choose item 2 because it is best to let the user know before any problems may arise.
This kind of OOC usage pattern comparison is popular with IP developers, but if IP is integrated into a large system, it is more troublesome, so you should avoid the first item.
This will also bring us the following problems:
What if the my_signal signal is only connected to the external output I/O?
For example, my_signal is connected to the I/O interface in all available cases, I want it to drive a tristate. I also want to be able to use OOC to synthesize this part of the module - while retaining the tristate
The way to meet the above requirements is to instantiate a tristate buffer in RTL.
The details are as follows:
OBUF u1(.l(din1), .T(n_enable), .O(my_signal));
This will ensure that my_signal will maintain a tristate value even with OOC synthesis.
At the same time, if the module is connected to other parts, then the connection is also unavailable (for example, the my_signal signal is connected to the "internal" module), and the integration process will report an error.
Air Core Inductor Coil,Ferrite Core Coil,Winding Air Core Inductors,Copper Induction Coil
IHUA INDUSTRIES CO.,LTD. , https://www.ihua-sensor.com