μPD795 characteristics, structure principle and drive timing

Single chip microcomputer STM32L151CCU6

Mobile phone crystal 3.2*2.5mm 3225 26M (26.000MHZ) 7.5PF 10PPM 20PPM 30PPM

Crystal oscillator

Photocoupler

1.1 μPD795 structure principle

The μPD795 is a linear CCD image sensor with high sensitivity, low dark current, built-in amplifier circuit and sample-and-hold circuit produced by NEC. It contains a column of 1,024 pixel photodiodes and two columns of 525-bit charge transfer registers. It can operate with 5 V drive (pulse) and 12 V power supply. At the same time, μPD795 has excellent photoelectric characteristics and high transfer efficiency, reaching 99.996%. It is mainly composed of three modules: a surface integration unit for generating a charge signal, a CCD shift register for charge signal transfer, and an output amplifier for converting a charge signal into a voltage signal.

The schematic diagram of the structure is shown in Figure 1. The package is in the form of a 20-pin DIP. The middle row is a photosensitive array consisting of photodiodes. The effective unit is 1,024 bits. Its function is to receive the external light signal and convert it into a corresponding charge signal. The two sides of the photosensitive array are the transfer gate and the charge transfer register. Under the action of the transmission gate clock signal φTGO, the photoelectric signals of the pixels are respectively transferred to the CCD transfer gates located on both sides thereof. Then, the charge signal in the MOS capacitor of the CCD is serially outputted from the output port by the action of φIO.

1.2 Drive Timing Analysis

The CCD device requires more than three drive timing pulses. Each drive pulse must strictly meet the phase timing requirements to ensure proper operation of the CCD device. The chip requires four pulses for normal operation, namely charge transfer register clock φIO, reset clock φRO, sample hold clock φSHO, and transfer gate clock φTGO. The timing relationship between them is shown in Figure 2.

The driving timing of CCD is a set of periodic and relatively complex pulse signals, which is an important factor affecting the signal processing capability, transfer efficiency, signal-to-noise ratio and other performance of CCD devices. The conventional drive circuit design has the following methods: the area array CCD usually adopts the corresponding dedicated drive IC, but it is difficult to debug, and can not be adapted to other CCD devices; the line array CCD can be driven by digital circuit and MCU I/O port. Or use programmable logic devices to complete the drive circuit design for the drive timing requirements of specific devices. In order to make the CCD device work under various light intensity signals, different integration time and corresponding driving pulse need to be set. The traditional single driving pulse can not meet the working requirements, and a circuit that can provide multiple driving pulses must be designed.

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