Abstract: Various reasons will prompt us to upgrade the 8051 design that used high-speed microcontrollers (DS80C310 / DS80C320 / DS80C323 / DS8xC520) to the new ultra-high-speed flash microcontrollers (DS89C430 / DS89C450). The reasons for product upgrades are: higher performance, value-added services and peripherals, and flexible internal flash memory. This application note discusses important differences between the two microcontroller families and explains how to upgrade from high-speed to ultra-high-speed devices.
Overview Maxim's high-speed microcontroller series includes a variety of different 8051 microcontrollers. Compared with the earlier 8051 12 clocks per machine cycle, they can achieve a higher speed of 4 clocks per machine cycle. Some high-speed microcontrollers fully utilize external program memory, such as the DS80C310; some controllers include internal EPROM or ROM program memory, such as the DS87C520 / DS83C520. These high-speed devices are pin compatible with existing 8051 microcontrollers, so in most cases, replacing a fast device and making very few software adjustments can easily upgrade the design.
In the same way, ultra-high-speed flash microcontrollers can replace high-speed microcontroller designs for upgrades. These new and more powerful microcontrollers include the DS89C430 / DS89C450. Important improvements include: expansion of the internal program flash memory (up to 64kB), the redesigned ultra-high-speed microcontroller core operates at a single clock cycle instruction, and the speed is the early 8051 design 12 times.
This application note discusses how to upgrade from a high-speed microcontroller to an ultra-high-speed flash memory device. It introduces the set of functions, pin changes, and SFR differences that must be considered when upgrading a design.
General references The programming guidelines for the following devices can be found in the high-speed microcontroller user guide (PDF, English only). DS80C310 High Speed ​​Microcontroller DS80C320 High Speed ​​Low Power Microcontroller DS80C323 High Speed ​​Low Power Microcontroller DS83C520 High Speed ​​ROM Microcontroller DS87C520 High Speed ​​EPROM Microcontroller Programming Guide for the following devices please refer to the Ultra High Speed ​​Flash Microcontroller User Guide (PDF , English only). DS89C430 Ultra High Speed ​​Flash Microcontroller DS89C450 Ultra High Speed ​​Flash Microcontroller Device Basic Functions Table 1. Device Function Comparison
Device pinout list 2. Differences in device pins
Device Register Table 3. SFR Map Comparison
Table 4. SFR function differences
Single-cycle instructions The ultra-high-speed DS89C430 / DS89C450 processors work in single-cycle instructions, and it takes only one clock cycle to execute an instruction. The DS80C310 / DS80C320 / DS80C323 / DS8xC520 high-speed processor requires four clock cycles to complete a machine cycle, compared to the speed Increase 4 times. The difference in clock speed means that using the DS89C430 / DS89C450 to replace high-speed devices at the same crystal frequency will increase the speed by 4 times.
The non-volatile memory DS80C310 / DS80C320 / DS80C323 has no internal program memory and requires external memory to store the program. DS8xC520 improved the memory scheme, including 16kB program EPROM.
When migrating from DS80C310 / DS80C320 / DS80C323 to DS89C430 / DS89C450, application programs stored in external ROM, flash memory, or EPROM memory can be relocated to the internal flash memory of the ultra-high-speed processor. The DS89C430 provides the same internal program memory (16kB) as the DS89xC520. All applications stored in the DS8xC520 can be placed in the DS89C430 without adjustment. For the application of external program memory, the program can be loaded into the 64kB internal flash memory of the DS89C450, as long as it does not occupy 64kB of program storage space for port expansion.
Finally, because the DS89C430 / DS89C450 supports the standard 8051 multiplexed address bus, external program memory can also be used when necessary.
Serial port loader Although the DS8xC520 contains internal EPROM program memory, it does not support in-system or in-application programming (IAP). The EPROM must be loaded with a separate programmer, and the DS8xC520 must be disconnected (or electrically isolated) from other circuits in the system when reprogramming (however, it is possible to design a user loader on the DS8xC520 to allow external programs or data EPROM Non-volatile RAM is reloaded under system control. For more information, please refer to Application Note 102, "Using the High-Speed ​​Microcontroller as a Bootstrap Loader")
The DS89C430 / DS89C450 adds a serial port loader, which improves the programming process. This function allows the program memory to reload the program through a simple ASCII-based protocol. The serial port loader is realized by the internal ROM of the microcontroller, and does not occupy the program space. In addition, the FCNTL and FDATA registers can be used for IAP, and part of the flash memory can be erased and rewritten under user control.
GPIO port 0 Since DS89C430 / DS89C450 (similar to DS8xC520) can work without external program and data storage, their 8 P0 ports (used as AD [7: 0] when the multiplexed bus is valid) can be used as general purpose I / O (GPIO). When the external bus is not used, there are some I / O pins that can be redefined as general purpose I / O: 8 P2 ports (P2 [7: 0]), P3.6 (nWR) and P3.7 (nRD) foot.
However, unlike P2 and P3, P0 uses an open-drain output driver. This means that if these ports are used as outputs, they must be connected to pull-up resistors. If the P0 port is used as an input (driven externally), no pull-up resistor is required.
1 frequency division clock The CKMOD register of the DS89C430 / DS89C450 adds the function that the system clock directly drives three timers (timer 0, timer 1, and timer 2) (different from the standard division by 4 and division by 12 options). This high-speed selection mode (controlled by the T0MH, T1MH, and T2MH bits) is disabled by default after reset to ensure that the timer is compatible with the DS80C310 / DS80C320 / DS80C323 / DS8xC520 program.
The crystal frequency doubler DS89C430 / SD89C450 contains an on-chip crystal frequency doubler, which can increase the crystal frequency by 2 or 4 times. This means that a 5MHz crystal can generate a 5MHz, 10MHz or 20MHz clock as needed.
5-level interrupt priority The DS89C430 / DS89C450 extend the programmable interrupt priority scheme and can specify a user-defined from 0 (lowest) to 3 (highest non-power supply) for any external interrupt, timer interrupt, serial port interrupt or watchdog interrupt Fault priority) interrupt level. The highest priority level 4 is reserved for power failure interruptions. This system is backward compatible with the low / high programmable priority scheme used by the DS80C310 / DS80C320 / DS80C323 / DS8xC520.
Power-supply considerations The DS89C430 / DS89C450 have improved processing power and have higher power-supply current requirements than high-speed microcontrollers. Under the maximum crystal frequency operating conditions, the DS89C430 / DS89C450 consumes 110mA (75mA typical) of the supply current. Therefore, when upgrading to DS89C430 / DS89C450, due to increased power consumption, it may be necessary to change the power supply circuit for high-speed design. For more details, please refer to the device data sheet.
Digital noise considerations The performance improvement of the ultra-high-speed flash memory Controller stems from the redesign of the core, which reduces the machine cycle and significantly increases the internal switching speed. For this reason, when directly replacing high-speed microcontrollers with ultra-high-speed flash microcontrollers, system designers can see a slight increase in digital noise. At this time, the designer should identify the factors that affect the performance improvement in the design. In some cases, it is necessary to add additional bypass capacitors to the microcontroller, or use other filtering methods to reduce digital noise.
Software timing loops When upgrading from high-speed microcontrollers to ultra-high-speed devices, applications that use software loops to generate precise timing may need adjustments. After upgrading to DS89C430 / DS89C450, because not all instructions are executed four times faster, this type of timed loop must be checked one by one. For example, on all high-speed microcontrollers, the "ADD A, R0" instruction requires 4 clock cycles to complete, while on the DS89C430 / DS89C450 it takes only one clock cycle to complete (the speed is increased by 4 times), the instruction "ADD A, @ R0 â€4 cycles are required on high-speed devices and 2 cycles on DS89C430 / DS89C450 (speed is increased by 2 times). For more information, please refer to the high-speed microcontroller user guide (English only) and the ultra-high-speed flash microcontroller user guide (English only) "Instruction Timing" section.
Overview Maxim's high-speed microcontroller series includes a variety of different 8051 microcontrollers. Compared with the earlier 8051 12 clocks per machine cycle, they can achieve a higher speed of 4 clocks per machine cycle. Some high-speed microcontrollers fully utilize external program memory, such as the DS80C310; some controllers include internal EPROM or ROM program memory, such as the DS87C520 / DS83C520. These high-speed devices are pin compatible with existing 8051 microcontrollers, so in most cases, replacing a fast device and making very few software adjustments can easily upgrade the design.
In the same way, ultra-high-speed flash microcontrollers can replace high-speed microcontroller designs for upgrades. These new and more powerful microcontrollers include the DS89C430 / DS89C450. Important improvements include: expansion of the internal program flash memory (up to 64kB), the redesigned ultra-high-speed microcontroller core operates at a single clock cycle instruction, and the speed is the early 8051 design 12 times.
This application note discusses how to upgrade from a high-speed microcontroller to an ultra-high-speed flash memory device. It introduces the set of functions, pin changes, and SFR differences that must be considered when upgrading a design.
General references The programming guidelines for the following devices can be found in the high-speed microcontroller user guide (PDF, English only). DS80C310 High Speed ​​Microcontroller DS80C320 High Speed ​​Low Power Microcontroller DS80C323 High Speed ​​Low Power Microcontroller DS83C520 High Speed ​​ROM Microcontroller DS87C520 High Speed ​​EPROM Microcontroller Programming Guide for the following devices please refer to the Ultra High Speed ​​Flash Microcontroller User Guide (PDF , English only). DS89C430 Ultra High Speed ​​Flash Microcontroller DS89C450 Ultra High Speed ​​Flash Microcontroller Device Basic Functions Table 1. Device Function Comparison
| Feature | DS80C310 | DS80C320 DS80C323 | DS87C520 DS83C520 | DS89C430 DS89C450 |
| Clocks per Machine Cycle | 4 | 4 | 4 | 1 |
| OperaTIng Voltage Range (V) | 4.5 to 5.5 | 4.25 to 5.5 (DS80C320) 2.7 to 5.5 (DS80C323) | 4.5 to 5.5 | 4.5 to 5.5 |
| Clock Rate (MHz, max) | 33 | 33 (DS80C320) 18 (DS80C323) | 33 | 33 |
| InstrucTIon ExecuTIon TIme (ns, min) | 121 | 121 (DS80C320) 222 (DS80C323) | 121 | 30 |
| Crystal Multiplier | √ (x2 or x4) | |||
| Ring Oscillator | √ | √ | √ | |
| Internal Program Memory | None | None | 16kB | 16kB (DS89C430) 64kB (DS89C450) |
| Internal Register Memory (Bytes) | 256 | 256 | 256 | 256 |
| Internal MOVX Memory | None | None | 1kB | 1kB |
| Serial Ports (UARTs) | 1 | 2 | 2 | 2 |
| External Interrupts | 6 | 6 | 6 | 6 |
| Port Pins (with Bus Active) | 16 | 16 | 16 | 16 |
| Port Pins (max) | 16 | 16 | 32 | 32 |
| Timer / Counters | Three / 16-bit | Three / 16-bit | Three / 16-bit | Three / 16-bit |
| Watchdog | √ | √ | √ | |
| Dual Data Pointers | √ | √ | √ | √ |
| Autoincrement / Decrement | √ | |||
| Stop Mode | √ | √ | √ | √ |
| Power-On Reset | √ | √ | √ | √ |
| Power-Fail Interrupt | √ | √ | √ |
Device pinout list 2. Differences in device pins
| DIP | PLCC | TQFP | DS80C310 | DS80C320 DS80C323 | DS87C520 DS83C520 | DS89C430 DS89C450 |
| 1 | 2 | 40 | P1.0 (T2) | P1.0 (T2) | P1.0 (T2) | P1.0 (T2) |
| 2 | 3 | 41 | P1.1 (T2EX) | P1.1 (T2EX) | P1.1 (T2EX) | P1.1 (T2EX) |
| 3 | 4 | 42 | P1.2 | P1.2 (RXD1) | P1.2 (RXD1) | P1.2 (RXD1) |
| 4 | 5 | 43 | P1.3 | P1.3 (TXD1) | P1.3 (TXD1) | P1.3 (TXD1) |
| 5 | 6 | 44 | P1.4 (INT2) | P1.4 (INT2) | P1.4 (INT2) | P1.4 (INT2) |
| 6 | 7 | 1 | P1.5 (nINT3) | P1.5 (nINT3) | P1.5 (nINT3) | P1.5 (nINT3) |
| 7 | 8 | 2 | P1.6 (INT4) | P1.6 (INT4) | P1.6 (INT4) | P1.6 (INT4) |
| 8 | 9 | 3 | P1.7 (nINT5) | P1.7 (nINT5) | P1.7 (nINT5) | P1.7 (nINT5) |
| 9 | 10 | 4 | RST | RST | RST | RST |
| 10 | 11 | 5 | P3.0 (RXD0) | P3.0 (RXD0) | P3.0 (RXD0) | P3.0 (RXD0) |
| 11 | 13 | 7 | P3.1 (TXD0) | P3.1 (TXD0) | P3.1 (TXD0) | P3.1 (TXD0) |
| 12 | 14 | 8 | P3.2 (nINT0) | P3.2 (nINT0) | P3.2 (nINT0) | P3.2 (nINT0) |
| 13 | 15 | 9 | P3.3 (nINT1) | P3.3 (nINT1) | P3.3 (nINT1) | P3.3 (nINT1) |
| 14 | 16 | 10 | P3.4 (T0) | P3.4 (T0) | P3.4 (T0) | P3.4 (T0) |
| 15 | 17 | 11 | P3.5 (T1) | P3.5 (T1) | P3.5 (T1) | P3.5 (T1) |
| 16 | 18 | 12 | P3.6 (nWR) | P3.6 (nWR) | P3.6 (nWR) | P3.6 (nWR) |
| 17 | 19 | 13 | P3.7 (nRD) | P3.7 (nRD) | P3.7 (nRD) | P3.7 (nRD) |
| 18 | 20 | 14 | XTAL2 | XTAL2 | XTAL2 | XTAL2 |
| 19 | twenty one | 15 | XTAL1 | XTAL1 | XTAL1 | XTAL1 |
| 20 | 22, 23 | 16, 17 | GND | GND | GND | GND |
| – | 1 | 39 | GND | N / C (can be connected to GND if desired) | GND | GND |
| twenty one | twenty four | 18 | A8 (P2.0) | A8 (P2.0) | A8 (P2.0) | A8 (P2.0) |
| twenty two | 25 | 19 | A9 (P2.1) | A9 (P2.1) | A9 (P2.1) | A9 (P2.1) |
| twenty three | 26 | 20 | A10 (P2.2) | A10 (P2.2) | A10 (P2.2) | A10 (P2.2) |
| twenty four | 27 | twenty one | A11 (P2.3) | A11 (P2.3) | A11 (P2.3) | A11 (P2.3) |
| 25 | 28 | twenty two | A12 (P2.4) | A12 (P2.4) | A12 (P2.4) | A12 (P2.4) |
| 26 | 29 | twenty three | A13 (P2.5) | A13 (P2.5) | A13 (P2.5) | A13 (P2.5) |
| 27 | 30 | twenty four | A14 (P2.6) | A14 (P2.6) | A14 (P2.6) | A14 (P2.6) |
| 28 | 31 | 25 | A15 (P2.7) | A15 (P2.7) | A15 (P2.7) | A15 (P2.7) |
| 29 | 32 | 26 | nPSEN | nPSEN | nPSEN | nPSEN |
| 30 | 33 | 27 | ALE | ALE | ALE | ALE / nPROG |
| 31 | 35 | 29 | nEA | nEA | nEA | nEA |
| 32 | 36 | 30 | AD7 | AD7 | AD7 (P0.7) | AD7 (P0.7) |
| 33 | 37 | 31 | AD6 | AD6 | AD6 (P0.6) | AD6 (P0.6) |
| 34 | 38 | 32 | AD5 | AD5 | AD5 (P0.5) | AD5 (P0.5) |
| 35 | 39 | 33 | AD4 | AD4 | AD4 (P0.4) | AD4 (P0.4) |
| 36 | 40 | 34 | AD3 | AD3 | AD3 (P0.3) | AD3 (P0.3) |
| 37 | 41 | 35 | AD2 | AD2 | AD2 (P0.2) | AD2 (P0.2) |
| 38 | 42 | 36 | AD1 | AD1 | AD1 (P0.1) | AD1 (P0.1) |
| 39 | 43 | 37 | AD0 | AD0 | AD0 (P0.0) | AD0 (P0.0) |
| 40 | 44 | 38 | VCC (+ 5V) | VCC + 5V (DS80C320) VCC + 3V (DS80C323) | VCC (+ 5V) | VCC (+ 5V) |
| – | 12 | 6 | N / C | N / C | N / C | VCC (+ 5V) |
| – | 34 | 28 | N / C | N / C | N / C | GND |
Device Register Table 3. SFR Map Comparison
| Address | DS80C310 | DS80C320 DS80C323 | DS87C520 DS83C520 | DS89C430 DS89C450 |
| 80h | – | – | P0 | P0 |
| 81h | SP | SP | SP | SP |
| 82h | DPL | DPL | DPL | DPL |
| 83h | DPH | DPH | DPH | DPH |
| 84h | DPL1 | DPL1 | DPL1 | DPL1 |
| 85h | DPH1 | DPH1 | DPH1 | DPH1 |
| 86h | DPS | DPS | DPS | DPS |
| 87h | PCON | PCON | PCON | PCON |
| 88h | TCON | TCON | TCON | TCON |
| 89h | TMOD | TMOD | TMOD | TMOD |
| 8Ah | TL0 | TL0 | TL0 | TL0 |
| 8Bh | TL1 | TL1 | TL1 | TL1 |
| 8Ch | TH0 | TH0 | TH0 | TH0 |
| 8Dh | TH1 | TH1 | TH1 | TH1 |
| 8Eh | CKCON | CKCON | CKCON | CKCON |
| 90h | P1 | P1 | P1 | P1 |
| 91h | EXIF | EXIF | EXIF | EXIF |
| 96h | – | – | – | CKMOD |
| 98h | SCON | SCON0 | SCON0 | SCON0 |
| 99h | SBUF | SBUF0 | SBUF0 | SBUF0 |
| 9Dh | – | – | – | ACON |
| A0h | P2 | P2 | P2 | P2 |
| A8h | IE | IE | IE | IE |
| A9h | SADDR0 | SADDR0 | SADDR0 | SADDR0 |
| AAh | – | SADDR1 | SADDR1 | SADDR1 |
| B0h | P3 | P3 | P3 | P3 |
| B1h | – | – | – | IP1 |
| B8h | IP | IP | IP | IP0 |
| B9h | SADEN0 | SADEN0 | SADEN0 | SADEN0 |
| BAh | – | SADEN1 | SADEN1 | SADEN1 |
| C0h | – | SCON1 | SCON1 | SCON1 |
| C1h | – | SBUF1 | SBUF1 | SBUF1 |
| C2h | – | – | ROMSIZE | ROMSIZE |
| C4h | – | – | PMR | PMR |
| C5h | STATUS | STATUS | STATUS | STATUS |
| C7h | – | TA | TA | TA |
| C8h | T2CON | T2CON | T2CON | T2CON |
| C9h | T2MOD | T2MOD | T2MOD | T2MOD |
| CAh | RCAP2L | RCAP2L | RCAP2L | RCAP2L |
| CBh | RCAP2H | RCAP2H | RCAP2H | RCAP2H |
| CCh | TL2 | TL2 | TL2 | TL2 |
| CDh | TH2 | TH2 | TH2 | TH2 |
| D0h | PSW | PSW | PSW | PSW |
| D5h | – | – | – | FCNTL |
| D6h | – | – | – | FDATA |
| D8h | WDCON | WDCON | WDCON | WDCON |
| E0h | ACC | ACC | ACC | ACC |
| E8h | EIE | EIE | EIE | EIE |
| F0h | B | B | B | B |
| F1h | – | – | – | EIP1 |
| F8h | EIP | EIP | EIP | EIP0 |
Table 4. SFR function differences
| SFR | Bit (s) | Differences |
| P0 | – | DS8xC520 / DS89C430 / DS89C450 only; controls Port 0 pins. |
| DPS | 4 (AID) | DS89C430 / DS89C450 only; controls the autoincrement / decrement function for the active data pointer. |
| 5 (TSL) | DS89C430 / DS89C450 only; enables automatic toggling between data pointers after certain opcodes. | |
| 6 (ID0) | DS89C430 / DS89C450 only; controls the effect of INC DPTR (increment or decrement) on DPTR. | |
| 7 (ID1) | DS89C430 / DS89C450 only; controls the effect of INC DPTR (increment or decrement) on DPTR1. | |
| PCON | 4 (OFDE) | DS89C430 / DS89C450 only; crystal oscillator fail detection enable. |
| 5 (OFDF) | DS89C430 / DS89C450 only; crystal oscillator fail detection flag. | |
| CKCON | 7 (WD1) 6 (WD0) | On all devices except the DS80C310; these bits control the watchdog timer period. |
| EXIF | 0 (BGS) | On all devices except the DS80C310; this bit enables / disables the bandgap reference during stop mode. |
| 1 (RGSL) | On all devices except the DS80C310; this bit controls execution from the ring oscillator during the crystal warmup period. | |
| 2 (RGMD) | On all devices except the DS80C310; this flag indicates the current clock source (ring or crystal). | |
| 3 | DS8xC520 (XT / nRG); selects the ring oscillator or crystal as the desired clock source. DS89C430 / DS89C450 (CKRY); indicates that the crystal oscillator or crystal multiplier has completed its warmup period. | |
| CKMOD | 3 (T0MH) | DS89C430 / DS89C450 only; allows Timer 0 to run directly from the system clock (clock / 1). |
| 4 (T1MH) | DS89C430 / DS89C450 only; allows Timer 1 to run directly from the system clock (clock / 1). | |
| 5 (T2MH) | DS89C430 / DS89C450 only; allows Timer 2 to run directly from the system clock (clock / 1). | |
| ACON | 5 (PAGES0) 6 (PAGES1) | DS89C430 / DS89C450 only; selects the page-mode configuration for external bus operations. |
| 7 (PAGEE) | DS89C430 / DS89C450 only; enables page mode (as opposed to the standard 8051 expanded bus mode) for external bus operations. | |
| IE | 6 (ES1) | On all devices except the DS80C310; this bit enables / disables the serial port 1 interrupt. |
| SADDR1 | – | On all devices except the DS80C310; this register controls the slave address for serial port 1. |
| IP1 | – | DS89C430 / DS89C450 only; this register combines with the settings in IP0 / IP to provide four priority-level settings for each interrupt (as opposed to two settings with IP only). |
| SADEN1 | – | On all devices except the DS80C310; this register sets the slave address mask for serial port 1. |
| SCON1 | – | On all devices except the DS80C310; this register controls mode settings for serial port 1. |
| SBUF1 | – | On all devices except the DS80C310; this register provides the input / output buffer for serial port 1. |
| ROMSIZE | 2: 0 (RMS2: 0) | DS8xC520 / DS89C430 / DS89C450 only; selects the range of on-chip EPROM / flash that maps into program space. |
| 3 (PRAME) | DS89C430 / DS89C450 only; enables / disables mapping of the 1kB internal RAM into program space. | |
| PMR | 1: 0 (DME1: ​​0) | DS8xC520 / DS89C430 / DS89C450 only; controls mapping of internal data memory into data space. |
| 2 | DS8xC520 (ALEOFF); when set to 1, disables ALE during on-board memory access. DS89C430 / DS89C450 (ALEON); when set to 0, disables ALE during on-board memory access. | |
| 3 | DS8xC520 (XTOFF); when set to 1, disables the crystal oscillator (must run from ring). DS89C430 / DS89C450 (4X / n2X); sets the mode for the crystal multiplier. | |
| 4 (CTM) | DS89C430 / DS89C450 only; when set to 1, enables the crystal multiplier. | |
| 5 (SWB) | DS8xC520 / DS89C430 / DS89C450 only; when set to 1, enables automatic switchback mode. | |
| 7: 6 (CD1: 0) | DS8xC520 / DS89C430 / DS89C450 only; controls the clock division or multiplier mode. Note that the available settings are different on the DS8xC520 / DS89C430 / DS89C450. | |
| STATUS | 0 (SPRA0) | DS8xC520 / DS89C430 / DS89C450 only; indicates that a character is currently being received on serial port 0. |
| 1 (SPTA0) | DS8xC520 / DS9C430 / DS89C450 only; indicates that a character is currently being transmitted on serial port 0. | |
| 2 (SPRA1) | DS8xC520 / DS89C430 / DS89C450 only; indicates that a character is currently being received on serial port 1. | |
| 3 (SPTA0) | DS8xC520 / DS89C430 / DS89C450 only; indicates that a character is currently being transmitted on serial port 1. | |
| 4 (XTUP) | DS8xC520 only; indicates whether the crystal oscillator has completed its warmup cycle. | |
| 5 (LIP) | DS80C320 / DS80C323 / DS8xC520 only; indicates that a low-priority interrupt is currently being serviced. | |
| 6 (HIP) | DS80C320 / DS80C323 / DS8xC520 only; indicates that a high-priority interrupt is currently being serviced. | |
| 7 (PIP) | DS80C320 / DS80C323 / DS8xC520 only; indicates that a power-fail priority interrupt is currently being serviced. | |
| 7: 5 (PIS2: 0) | DS89C430 / DS89C450 only; indicates that the priority level of the interrupt is being serviced. | |
| TA | – | On all except the DS80C310; controls the Timed Access register protection mechanism. |
| WDCON | 0 (RWT) | On all devices except the DS80C310; resets the watchdog timer. |
| 1 (EWT) | On all devices except the DS80C310; enables / disables the watchdog timer. | |
| 2 (WTRF) | On all devices except the DS80C310; indicates that a watchdog timer reset has occurred. | |
| 3 (WDIF) | On all devices except the DS80C310; indicates that a watchdog timer interrupt has occurred. | |
| 4 (PFI) | On all devices except the DS80C310; indicates that a power-fail interrupt has occurred. | |
| 5 (EPFI) | On all devices except the DS80C310; enables / disables the power-fail interrupt. | |
| 6 (POR) | On all devices; indicates that a power-on reset has occurred. | |
| 7 (SMOD_1) | On all devices except the DS80C310; enables / disables baud-rate doubling mode for serial port 1. | |
| EIE | 4 (EWDI) | On all devices except the DS80C310; enables / disables interrupts from the watchdog timer. |
| EIP | 3: 0 (PX5: 2) | On all devices except the DS89C430 / DS89C450; sets high / low priority for external interrupts 2, 3, 4, and 5. |
| 4 (PWDI) | DS80C320 / DS80C323 / DS8xC520 only; sets high / low priority for the watchdog timer interrupt. | |
| EIP1, EIP0 | – | DS89C430 / DS89C450 only; these registers set priority levels 0–3 for the watchdog timer interrupt and external interrupts 2, 3, 4, and 5. |
Single-cycle instructions The ultra-high-speed DS89C430 / DS89C450 processors work in single-cycle instructions, and it takes only one clock cycle to execute an instruction. The DS80C310 / DS80C320 / DS80C323 / DS8xC520 high-speed processor requires four clock cycles to complete a machine cycle, compared to the speed Increase 4 times. The difference in clock speed means that using the DS89C430 / DS89C450 to replace high-speed devices at the same crystal frequency will increase the speed by 4 times.
The non-volatile memory DS80C310 / DS80C320 / DS80C323 has no internal program memory and requires external memory to store the program. DS8xC520 improved the memory scheme, including 16kB program EPROM.
When migrating from DS80C310 / DS80C320 / DS80C323 to DS89C430 / DS89C450, application programs stored in external ROM, flash memory, or EPROM memory can be relocated to the internal flash memory of the ultra-high-speed processor. The DS89C430 provides the same internal program memory (16kB) as the DS89xC520. All applications stored in the DS8xC520 can be placed in the DS89C430 without adjustment. For the application of external program memory, the program can be loaded into the 64kB internal flash memory of the DS89C450, as long as it does not occupy 64kB of program storage space for port expansion.
Finally, because the DS89C430 / DS89C450 supports the standard 8051 multiplexed address bus, external program memory can also be used when necessary.
Serial port loader Although the DS8xC520 contains internal EPROM program memory, it does not support in-system or in-application programming (IAP). The EPROM must be loaded with a separate programmer, and the DS8xC520 must be disconnected (or electrically isolated) from other circuits in the system when reprogramming (however, it is possible to design a user loader on the DS8xC520 to allow external programs or data EPROM Non-volatile RAM is reloaded under system control. For more information, please refer to Application Note 102, "Using the High-Speed ​​Microcontroller as a Bootstrap Loader")
The DS89C430 / DS89C450 adds a serial port loader, which improves the programming process. This function allows the program memory to reload the program through a simple ASCII-based protocol. The serial port loader is realized by the internal ROM of the microcontroller, and does not occupy the program space. In addition, the FCNTL and FDATA registers can be used for IAP, and part of the flash memory can be erased and rewritten under user control.
GPIO port 0 Since DS89C430 / DS89C450 (similar to DS8xC520) can work without external program and data storage, their 8 P0 ports (used as AD [7: 0] when the multiplexed bus is valid) can be used as general purpose I / O (GPIO). When the external bus is not used, there are some I / O pins that can be redefined as general purpose I / O: 8 P2 ports (P2 [7: 0]), P3.6 (nWR) and P3.7 (nRD) foot.
However, unlike P2 and P3, P0 uses an open-drain output driver. This means that if these ports are used as outputs, they must be connected to pull-up resistors. If the P0 port is used as an input (driven externally), no pull-up resistor is required.
1 frequency division clock The CKMOD register of the DS89C430 / DS89C450 adds the function that the system clock directly drives three timers (timer 0, timer 1, and timer 2) (different from the standard division by 4 and division by 12 options). This high-speed selection mode (controlled by the T0MH, T1MH, and T2MH bits) is disabled by default after reset to ensure that the timer is compatible with the DS80C310 / DS80C320 / DS80C323 / DS8xC520 program.
The crystal frequency doubler DS89C430 / SD89C450 contains an on-chip crystal frequency doubler, which can increase the crystal frequency by 2 or 4 times. This means that a 5MHz crystal can generate a 5MHz, 10MHz or 20MHz clock as needed.
5-level interrupt priority The DS89C430 / DS89C450 extend the programmable interrupt priority scheme and can specify a user-defined from 0 (lowest) to 3 (highest non-power supply) for any external interrupt, timer interrupt, serial port interrupt or watchdog interrupt Fault priority) interrupt level. The highest priority level 4 is reserved for power failure interruptions. This system is backward compatible with the low / high programmable priority scheme used by the DS80C310 / DS80C320 / DS80C323 / DS8xC520.
Power-supply considerations The DS89C430 / DS89C450 have improved processing power and have higher power-supply current requirements than high-speed microcontrollers. Under the maximum crystal frequency operating conditions, the DS89C430 / DS89C450 consumes 110mA (75mA typical) of the supply current. Therefore, when upgrading to DS89C430 / DS89C450, due to increased power consumption, it may be necessary to change the power supply circuit for high-speed design. For more details, please refer to the device data sheet.
Digital noise considerations The performance improvement of the ultra-high-speed flash memory Controller stems from the redesign of the core, which reduces the machine cycle and significantly increases the internal switching speed. For this reason, when directly replacing high-speed microcontrollers with ultra-high-speed flash microcontrollers, system designers can see a slight increase in digital noise. At this time, the designer should identify the factors that affect the performance improvement in the design. In some cases, it is necessary to add additional bypass capacitors to the microcontroller, or use other filtering methods to reduce digital noise.
Software timing loops When upgrading from high-speed microcontrollers to ultra-high-speed devices, applications that use software loops to generate precise timing may need adjustments. After upgrading to DS89C430 / DS89C450, because not all instructions are executed four times faster, this type of timed loop must be checked one by one. For example, on all high-speed microcontrollers, the "ADD A, R0" instruction requires 4 clock cycles to complete, while on the DS89C430 / DS89C450 it takes only one clock cycle to complete (the speed is increased by 4 times), the instruction "ADD A, @ R0 â€4 cycles are required on high-speed devices and 2 cycles on DS89C430 / DS89C450 (speed is increased by 2 times). For more information, please refer to the high-speed microcontroller user guide (English only) and the ultra-high-speed flash microcontroller user guide (English only) "Instruction Timing" section.
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