How to consolidate integration and reuse coverage while developing IP? Some functions and performances of IP can be configured. It is necessary to consider whether IP can be normalized after various reasonable configurations. The function coverage is first organized into a hierarchical abstract function coverage model called cover model. .
This is a paper on how to consider reuse coverage when IP development. As far as hardware design IP is concerned, we are only implementing IP or integrating IP. As far as the current situation is concerned, the implementation of IP is increasingly concentrated in large companies. On the one hand, they have more experience to ensure that configurable IP can meet various user needs, and on the other hand, because of their deep customer base, high-quality IP R&D costs and a large amount of silicon-proven can be formed. Good business development. At present, most companies use commercial IP on important IPs, which comes from many considerations. As Verifier, there may be more opportunities to go to a SoC company to perform validation on custom modules, core knowledge modules or IP modules. At least one-third of the SoC's work is integrated verification of IP modules. SoC verifier looks at IP more from the perspective of integrated verification.
The perspective of this excerpt from this paper is from the perspective of IP development. Just taking this opportunity, Xiaobian can freely sort out the process of IP development in both design and verification. Since the article uses PCIe as an example, my next description of the IP development process and the integration verification process is also based on PCIe.
For a mature PCIe IP, a commercial IP company might sell its hardware design IP, possibly sell its verification IP, or both. For example, Synopsys sells its design IP and verification IP at the same time, which means that this large IP department store will sell you a design solution, and will also recommend you to purchase a verification solution for his home. Whether designing or verifying, you first need a PCIe functional mode configuration. This configuration is based on the architecture of the SoC. From the previous architecture research, the appropriate functions, performance, and power consumption parameters are selected. Both Designer and Verifier will use this configuration file to generate a custom design IP or verification IP. Then the paired design IP and verification IP can be set up in the test environment, and then the IP level or SoC level verification work can be performed. But in the process of verification, how do we complete verification quantification at the IP and SoC levels? This is certainly inseparable from coverage, especially functional coverage. But often the functional coverage is not generated along with the design IP or the verification IP. Why? In fact, it is still related to the highly configurable IP itself. In this paper, the PCIe design IP is taken as an example to illustrate the difficulty of defining functional coverage for configurable IP.
Since some functions and performance of IP are configurable, for example, some functions may be disabled (static) after configuration, and some functions may be disabled (dynamic) through the configuration of the emulator, so these differences The configuration poses a challenge to defining a common functional coverage model. From the article, PCIe IP developers are already annoyed when verifying, because they face more challenges than SoC verifier, the former needs to consider all configuration possibilities, while the latter only need to choose a limited configuration for integration verification. Or to say that the former needs to consider whether IP can be normal after various reasonable configurations, and the latter needs to consider whether IP can be well integrated into the system after being integrated by SoC.
One problem with IP integration is that IP providers don't know if IP is integrated correctly when it is integrated by various customers; IP users also have almost their own reliability for IP generation, at the IP system level and SoC level. There is a vague understanding of test coverage. The obstacle between the two sides comes from the fact that they lack a clear data to indicate the completion of the test. From this article, if an IP provider can generate custom feature coverage while generating custom IP, then such a coverage rate is for the IP developer to verify the IP itself, or the IP integrator. Instructive help is provided when verifying the integration of IP.
So is there such a functional coverage that can be customized with the IP profile? This article gives a solution. From the final conclusions of this article, the configurable feature coverage will be associated with each configured IP, and when testing so many IP configurations, developers can use these feature coverage to measure The verification of IP is complete. If such a functional coverage can be handed over to the SoC integrator along with the IP, IP and SoC-level verification can be integrated to collect feedback on this functional coverage model. This way, if IP providers and integrators are all based on the same functional coverage model, it will be easier to review the functional testing and integration of IP together.
The following is a small series outlining how this paper implements the custom coverage of highly configurable IP.
The functional coverage is first organized into a hierarchical abstract functional coverage model called cover model.
The abstract coverage model consists of multiple block models. The important functions represented by these block models are finally combined to form the overall functional situation, namely the cover model.
For the respective tree structure of the block model, each tree end constitutes an overlay variable, cover variable. But these overlay variables do not point to specific signals, but still abstractly describe the range of functions and relationships they are testing.
With cover variables, you can place them or cross-generate new coverage, called cover group.
The underlying cover variable and cover group contained in these tree-like coverage models are included in the Excel spreadsheet. Accompanying them, there are configuration variables. Configuration variables are important because different settings may determine the range of values ​​for some cover variables, or whether there are certain cover variables.
The hierarchically placed Excel spreadsheet is read by the Perl script and produces a hierarchical SystemVerilog covergroup. These covergroups are also accompanied by a block model, which corresponds to each function, forming a hierarchical relationship, and finally as a customized cover model.
This paper coincides with some of the ways I now do to define functional coverage at the SoC level. First, functional coverage needs to have an abstract functional definition before precipitation, so different functions can be used as independent block models. The complex function can be further disassembled into a child block model, and finally it can not be split into pieces, so the point that cannot be split is the cover variable. Maybe some companies are accustomed to deploy functional test points in plain text, which will also be the tiled SV cover group definition; if you define the function points, you can get it from the Excel table. With the guarantee of script processing, you can split the design into several functions at first, and then use the hierarchical method to define the block model at the sub-level.
What are the advantages of a tree-like coverage model compared to a tiled coverage model? It is easy to do review and coverage analysis. For the IP verification in this paper, the tree structure also facilitates the hierarchical delivery of some variables and the targeted processing of scripts. From the perspective of reuse, if the scripting process of Excel to SV cover group is implemented, the function point splitting of the tree structure is also beneficial for future maintenance, such as deleting a node from the tree structure and below. All sub-nodes (ie, deleting a certain function), for example, grafting the IP-level coverage tree structure into the coverage tree structure of the SoC system, making it a certain one of them, are all feasible methods.
ConclusionThe automation of Excel to SV cover group is a suitable direction, but in the implementation process, it is also necessary to clarify how to abstract the abstract function point test to each cover group. For example, functional point tests may have included relationships. For example, some function point tests may still be too abstract and need further subdivision. This paper uses a script combined with IP configuration variables in Excel to generate a hierarchical functional coverage model. It is a good try. This coverage, if it can go from the IP level to the SoC level, will be a better measure of IP integration testing.
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