I. Overview
This article describes a keyboard circuit and driver design using the MAX7348's serial I2C bus.
I2C requires less wiring and only requires one serial clock line and one serial data line. It has been widely used because it allows multi-master control, has ruling and synchronization functions, and can add or remove sub-devices on the bus at will.
Second, MAX7348
United States is produced by MAXIM MAX7348 2-wire interface, keyboard switches and low EMI sound controller can monitor up to 40 buttons can debounces and stored in the FIFO, the user can debounce time between 9 ~ 40ms Arbitrarily set, the MAX7348's own tone generator can automatically generate button sound and alarm sound under the action of the controller. During the sound generation, the output can also be set to high level or low level to drive the electronic sounder, relay or Indicator light.
The chip adopts 400Kps, 5.5V tolerance 2-wire serial interface, working voltage 2.4 ~ 3.6V, 4 I2C address selection. Also in the same series as the MAX7348 are the MAX7347 and MAX7349.
Pin diagram
As shown in Figure 1, SDA and SCL are data and clock interfaces compatible with the I2C serial bus. They usually need to be connected to a pull-up resistor with a typical value of 4.7kΩ. ROW0 ~ ROW8 are keyboard matrix row input ports. Open circuit; COL0 ~ COL4 is the keyboard matrix column output port; SOUNDER is the sounder output port, the output is push-pull structure, usually connected with a piezoelectric ceramic piece or other sounding device; INT is the interrupt output port; ADO is the address input port, to the address provided from the device, which pin is connected to GND, V +, SDA, SCL may be formed in four types of logical combinations thereof MAX7348 four optional I2C address, as shown in table 1; GND ground terminal, V + then Power supply (2.4 ~ 3.6V).
Table 1 2-wire interface address allocation table
2. Main internal register
(1) Key FIFO Register (00H) This register contains information about keys FIFO states associated, as well as those after the event information debounced, those keys D0 ~ D5 indicates the key of this register that have been debounced, D6 indicate the current to Whether the dither button is the last one in the FIFO; the D7 bit is the overflow flag, which indicates whether the button FIFO overflows. Reading the key scan FIFO will clear the interrupt signal, but the interrupt (INT) signal will only be generated again by clearing the FIFO by performing a sufficient number of read operations.
(2) Debounce register (01H) This register is used to set each of a debounce time period, and the enabling and disabling GPO port, wherein D0 ~ D4 bits are used in the range of 9 ~ 40ms debounce time is set, step 1ms, D5 ~ D7 is used to set which GPO port is enabled (Table 2).
Table 2 Debounce Register Settings
(3) Auto Repeat Register ( 02H) This register is used to set the auto repeat frequency and its delay. The auto repeat function allows continuous triggering of key events when the button is pressed and not released. The automatic repeat delay specifies the time between the first press of the button and the start of the repeat (if the button is not released). The automatic repetition frequency specifies the speed at which the key event is continuously triggered after the automatic repeat starts. D0 ~ D3 set the automatic repeat delay, ranging from 8 debounce cycles to 128 debounce cycles. The D4 ~ D6 bits specify the repetition rate in the range of 4 to 32 debounce periods, and the D7 bit is the auto-repeat enable bit (as shown in Table 3).
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